1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the invention relates to a semiconductor memory device capable of providing a plurality of product families.
2. Description of Related Art
In recent years, due to the increase of a frequency of a clock signal driving a synchronous DRAM (SDRAM), the data transfer rate (bandwidth) of the synchronous DRAM has been remarkably improved. In an SDRAM compliant with the DDR3 (Double Data Rate3) specification, the maximum clock frequency has reached 800 MHz, and a data transfer rate per DQ pin has reached 1.6 Gbp/s. Accordingly, even in one chip where the number of DQ pins is 4 bytes=32 pins, a bandwidth of 6.4 GB/s may be obtained.
On the other hand, the improvement in an operation speed of a memory cell array arranged in a DRAM core is rather slow in comparison with the improvement in the operation clock frequency. In order to achieve a high data transfer rate, there is such a measure as to increase the number of bits to be read (prefetched) from the array simultaneously.
According to the DDR3 specification, prefecthing of eight bits per DQ pin is performed, and the prefetched bits are subjected to parallel-to-serial conversion by a serializer and are consecutively output (burst read).
In case of writing, as well, data of eight bits per DQ pin is consecutively received (burst written), and the received data is subjected to serial-to-parallel conversion by a deserializer, and the parallel eight bits are simultaneously written to the memory array.
The eight-bit consecutive access (burst access) described above is executed by a one-time request for reading from the SDRAM or a one-time request for writing to the SDRAM.
For this reason, with the configuration having 32 DQ pins (which is an x32 configuration), a data amount to be read or written by one access becomes four bytes (=32 bits)×eight-bit burst access=32 bytes.
This is a large value, as an amount of one-time data transfer between a microprocessor and a main memory. A lot of applications need a data transfer amount which is smaller than this data transfer amount.
There has been used a microprocessor or a microcontroller which includes a plurality of CPU cores. Each core independently executes a different task. Thus, even if a data transfer amount for one core is not large, a large amount of data transfer is needed for an overall multi-core processor.
Further, there arises the need for performing data transfer to different regions on a main memory assigned to respective cores.
Such a request cannot be satisfied by specifications provided by a conventional DRAM.    [Patent Document 1]
JP Patent Kokai Publication No. JP-A-08-111088    [Patent Document 2]
JP Patent Kokai Publication No. JP-P2000-11641A    [Patent Document 3]
JP Patent Kokai Publication No. JP-P2000-68441A    [Patent Document 4]
JP Patent Kokai Publication No. JP-P2003-242800A    [Patent Document 5]
US2006/0117155A1